1. Field of the Invention
Embodiments of the present invention generally relate to a method of barrier layer formation and, more particularly to a method of integrated barrier layer formation using both cyclical deposition techniques and chemical vapor deposition techniques.
2. Description of the Background Art
In the manufacture of integrated circuits, contact level metallization schemes are often used to provide low resistance contacts to an underlying semiconductor material. Typically, contact level metallization schemes combine an integrated barrier layer with a contact level metal layer.
For example, when a gate electrode of a transistor is fabricated, an integrated barrier layer (e.g., titanium nitride/tungsten (TiN/W)) is formed between the gate material (e.g., polysilicon) and the contact level metal layer (e.g., aluminum (Al) or copper (Cu)) of the gate electrode. The integrated barrier layer inhibits the diffusion of the aluminum (Al) or copper (Cu) into the polysilicon gate material. Such aluminum (Al) or copper (Cu) diffusion is undesirable because it potentially changes the characteristics of the transistor, rendering the transistor inoperable.
The integrated barrier layer typically comprises two different material layers. Each of the material layers is typically formed using a separate process chamber. For example, separate deposition chambers may be used for depositing the titanium nitride (TiN) layer and the tungsten (W) layer comprising a titanium nitride/tungsten (TiN/W) integrated barrier layer. The separate deposition chambers may include, for example, physical vapor deposition (PVD) chambers and/or chemical vapor deposition (CVD) chambers. However, the use of separate deposition chambers to form each material layer comprising the integrated barrier layer is costly.
Additionally, as circuit densities increase, the widths of integrated circuit features such as, for example, gate electrodes, may decrease to sub-micron dimensions (e. g., less than 0.25 micrometers), whereas the thickness of material layers between such features typically remains substantially constant, increasing the aspect ratios therefor. The term aspect ratio as used herein refers to the ratio of the feature height divided by the feature width. Many traditional deposition processes have difficulty filling sub-micron features where the aspect ratio exceeds 8:1, and especially where the aspect ratio exceeds 10:1.
FIG. 1 illustrates the possible consequences of material layer deposition in a high aspect ratio feature 6 formed on a substrate 1. The high aspect ratio feature 6 may be any opening such as a space formed between adjacent features 2, a contact, a via, or a trench defined in a material layer. As shown in FIG. 1, a material layer 11 that is formed using conventional deposition techniques (e.g., chemical vapor deposition (CVD) and/or physical vapor deposition (PVD)) tends to be deposited on the top edges 6T of the feature 6 at a higher rate than at the bottom 6B or sides 6S thereof creating an overhang. This overhang or excess deposition of material is sometimes referred to as crowning. Such excess material continues to build up on the top edges 6T of the feature 6, until the opening is closed off by the deposited material 11, forming a void 4 therein. The presence of voids may result in unreliable integrated circuit performance.
Therefore, a need exists for a system and method for forming integrated barrier layer structures.